RISC-V Verification IP
- RISCV-DV Covering all ISA Extensions
- Highly Structured and Customizable
- Generates Binary Dump Directly
- HPC-Powered, Multicore-Enabled
- Completely Opensource and Free
HW/SW Coverification
- Randomize TLM2 Payloads Natively
- Run UVM Testbench on Embedded Boards
- Make Native OS Calls from Testbench
- Embed SW Drivers into UVM Testbenches
- Qemu-Driven Hardware Verification
FPGA-Powered Co-Emulation
- The World's Fastest HPC-Powered UVM
- 360 Degrees Portable Stimulus
- Zero Overhead C/C++ ABI Compatibility
- Pass UVM Stimulus Directly to FPGA
- Execute UVM Testbench on an SoCFPGA